The present invention relates to a semiconductor package, such as a wafer level CSP (Chip Size/Scale Package), using no wiring board (interposer), a semiconductor device, an electronic device, and a method for producing the semiconductor package; and particularly to a semiconductor package, a semiconductor device and an electronic device which can be produced with ease, and a method for producing the semiconductor package.
In recent years, a development of small-sized semiconductor devices has been promoted. With this development, attention is paid to the miniaturization of the packages of these semiconductor devices. For instance, a variety of semiconductor packages have been proposed in the August issue (1998) and February issue (1999) of Nikkei Micro-device. Among these packages, especially a wafer level CSP using a semiconductor package called CSP has a high effect on the miniaturization of a package and a reduction in costs. This CSP is a package resin-sealed together with a wafer. FIG. 15 is a sectional view showing the structure of a conventional CSP. Incidentally, FIG. 15 shows the condition that the above CSP will be mounted on a printed circuit board and the vertically positional relation between the parts explained hereinafter is reversed with respect to those of FIG. 15.
In the conventional CSP, plural electrodes, for example, Al pads 52 are formed on a wafer 51. Also a passivation film, for example, a SiN layer 53 and a polyimide layer 54 which cover the Al pads 52 are formed on the entire surface of the wafer 51. In the SiN layer 53 and the polyimide layer 54, a via hole which reaches the Al pad 52 from the surface of the polyimide layer 54 is formed and a conductive layer 55 is embedded in the via hole. On the polyimide layer 54, a rerouting layer 56 connected to the conductive layer 55 is formed. The rerouting layer 56 is formed of, for example, Cu. A sealing resin layer 57 coating the rerouting layer 56 is formed on the entire surface of the polyimide layer 54. Inside the sealing resin layer 57, a Cu post 58 which reaches the rerouting layer 56 from the surface of the sealing resin layer 57 is formed as a metal post. A barrier metal layer 59 is formed on the Cu post 58 and a solder ball 60 such as a solder is formed on the barrier metal layer 59.
Next, a method for producing the conventional CSP as mentioned above will be explained. FIGS. 16(a) to (e) are sectional views showing the method for producing the conventional CSP in step order. Incidentally, the rerouting layer, the polyimide layer and the like are omitted in FIGS. 16(a) to (e).
Firstly, as shown in FIG. 16(a), a wafer 61 with a flat surface is prepared. As shown in FIG. 16(b), plural Cu posts 62 are formed on the wafer 61 by plating. Next, as shown in FIG. 16(c), all Cu posts 62 are resin-sealed such that they are encased to form a sealing resin layer 63. Then, as shown in FIG. 16(d), the surface of the sealing resin layer 63 is polished to expose each Cu post 62. Thereafter, as shown FIG. 16(e), a solder ball 64 such as a solder is mounted on each Cu post 62.
The CSP as described above is thus formed. This CSP is made into a given size by dicing afterwards.
Since a semiconductor package is in general different from a printed circuit board or the like in thermal expansion coefficient, a stress based on the difference in thermal expansion coefficient focuses on a terminal of the semiconductor package. However, in the above-mentioned CSP, the stress is easily dispersed by making the cylindrical Cu post 62 have a large height.
However, in order to disperse the stress based on the difference in thermal expansion coefficient, it is necessary for a metal post, such as a Cu post, to have a height as large as about 100 xcexcm from the rerouting layer. However, if a metal post having such a height is formed by plating, there is a problem that a remarkable long period of time is required. This further gives rise to the problems of increased production cost and a difficulty in control of the height of the metal post.
In light of such problems, the present invention has been made. It is an object of the present invention to provide a semiconductor package, a semiconductor device and an electronic device which make it possible to disperse a stress produced when the package is mounted on a printed circuit board or the like and which can be produced for a short time, and a method for producing the semiconductor package.
A semiconductor package according to the present invention comprises: an insulating layer formed on a wafer that is provided with an electrode; a rerouting layer penetrating through said insulating layer, the one end of said rerouting layer being connected to said electrode; a sealing resin layer which seals said wafer, said insulating layer and said rerouting layer; a columnar resin material which is defined by making a ring-like opening portion in a resin layer constituting said sealing resin layer-and which is formed on said rerouting layer; and a conductive layer which is formed around said columnar resin material to cover said columnar resin material and which penetrates through said sealing resin layer to conduct electricity between a solder bump and the other end of said rerouting layer.
The present invention is provided with the columnar resin material covered with the conductive layer for conducting electricity between the solder bump and the other end of the rerouting layer, and the post is composed of the columnar resin layer and the conductive layer. This portion acts as a stress-relieving portion. Therefore, in the case that stress is generated in this portion, the stress is dispersed mainly by the columnar resin material. For this reason, no thick plating layer is necessary for the post. As a result, the process of the production is shortened. Since the height of the post can be controlled by the height of the columnar resin material, the adjustment thereof is easy.
The stress can be concentrated still more into the post by forming a resin layer having an opening portion formed only on a portion of said conductive layer, said portion covering an upper surface of said columnar resin material on said sealing resin layer.
Moreover, the damage of the rerouting layer when the ring-like opening portion is made can be reduced by forming a metal layer having a higher reflectivity against a laser used when said ring-like opening portion is formed than said rerouting layer on said rerouting layer and at least at a position conformable to said ring-like opening portion.
Another semiconductor package according to the present invention comprises a wafer that is provided with an electrode; and a post formed on said wafer, wherein said post comprises a resin material and a conductive layer formed at least on an upper surface of said resin material, a spherical solder bump is formed on said conductive layer positioned on an upper surface of said post, and the central position of said solder bump is consistent with the central position of said post as are viewed in plan.
In the present invention, since the post is provided with the conductive layer and the resin material, stress acting on this post is relieved by the resin material. Since the central position of the solder bump is consistent with the central position of the post as are viewed in plan, the stress is substantially uniformly dispersed and the distribution thereof is made uniform.
The electrode and the conductive layer may be connected to each other, and a part of the conductive layers may not be connected to the electrode. In other words, a part of the conductive layers are not connected to the electrode, and the post having the conductive layer is formed only to disperse the stress in the whole of the package uniformly.
The semiconductor device provided with any one of the above-mentioned semiconductor packages according to the present invention comprises an integrated circuit formed in the wafer.
The electronic device provided with this semiconductor device according to the present invention comprises a circuit board connected to the solder bump.
A method for producing a semiconductor package according to the present invention comprises the steps of: forming an insulating layer on a wafer that is provided with an electrode; forming a rerouting layer penetrating through said insulating layer, the one end of said rerouting layer being connected to said electrode; forming a sealing resin layer on the entire surface; making a ring-like opening portion reaching said rerouting layer in said sealing resin layer; forming a conductive layer from inside of said opening portion to upper side of said sealing resin layer, thereby making a shape that said sealing resin layer remaining inside said opening portion is covered with said conductive layer; and forming a solder bump on said conductive layer.
By using a laser to nake the opening portion, the side surface of the remaining resin layer is inclined toward the surface thereof. Thus, it is easy to form the conductive layer afterwards.
The sealing resin layer may be composed of a photosensitive resin, and the step of making the opening portion may be a step of making the opening portion by photolithography.